Silicon Germanium (SiGe) alloy has been used in non-recessed source/drain regions (such as raised source/drain) for a shallow junction to suppress the short channel effect. The short channel effect is a well-known phenomenon in which the threshold voltage becomes less predictable as the gate dimensions are reduced.
U.S. patent application No. 2003/0080361 describes a process for manufacturing an improved PMOS transistor. Recesses are etched into a layer of epitaxial silicon after formation of spacers adjacent the gate electrode, and implantation of dopant. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon after spacer formation. The alloy has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. Silicon under a biaxially stressed film, such as SiGe, enhances carrier mobility to improve current performance.
However, the short channel effect was increased as a result of the higher temperature conditions of epitaxially forming the silicon/geranium alloy in the source drain regions. An improved fabrication method that can improve device performance and the processing window is desired.